The project CROSSCON ended successfully on 31 October 2025 after three years of work where the R&D Spain team has acted as the coordinator, the leader of Work Package 1 on Requirements and Validation Criteria, and the leader of Work Package 6 on Dissemination, Exploitation and Impact Creation.

The final review with the EC took place online on December 17, in which our colleagues presented the project's activities and results. The Project Officer and the reviewers gave positive feedback, expressing that they would recommend the project as an example for best practice.

Main results: 

• The CROSSCON IoT Security Stack: an open source, portable, modular, and vendor-independent IoT security stack solving existing interoperability problems and implementing a trusted baseline and root of trust (RoT) across the different devices with heterogeneous embedded hardware architectures, including but not limited, to ARM and RISC-V.
• The CROSSCON Hypervisor: a low-level IoT device hypervisor supporting both APU and MCU platforms, including features like Dynamic VM creation and management, per-VM TEE support, and Multiple-VMM support.
• The CROSSCON SoC: a system on chip used together with the CROSSCON stack to provide a RISC-V execution environment for mixed criticality software that needs strong hardware and software isolation.
• The novel and high-assurance trusted services, such as second factor authentication – the PUF‐based and context‐based authentication, the control flow integrity, and the behavioural‐based anomaly detection.

Other important assets are the TEE-like environment on FPGAs with multiple tenants, Bare metal TEEs to provide essential security features for low constrained devices, etcetera.

More info:

The CROSSCON GitHub repository offers the release of the main software and hardware artefacts. Links to the main artefacts can also be found at the correspondent section on the project's website

Ambitious use case demonstrators on i) Device multi-factor authentication, ii) Firmware updates, iii) Commissioning and decommissioning of IoT devices, iv) Remote attestation for agricultural UAVs, and v) IP Protection for multi-tenancy on FPGA are described on the project's newsletter, issue 5.

The consortium participated in several RISC-V working groups and industrial events such as RISC-V Summit and Embedded World, established synergies with 16 EU-funded projects, achieved 50+ scientific publications, and contributed to 55 events. R&D Spain's contribution focused on

• Know-how generation and networking with stakeholders in this domain.
• Enabling the asset L-DAS on the Edge, i.e. on small form factor IoT platforms, such as Raspberry Pi 4b/5. Successfully optimized (quantized) the L-ADS deep learning models for efficient processing on such platforms ARM Cortex-A72/76, as well as on RISC-V (PoC on a Xilinx Arty Z7 board). For more information visit Zenodo.